library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity REGMUX_logic is
    port(SR1val: in unsigned(15 downto 0);
         BUS_in: in unsigned(15 downto 0);
         IR_out: in unsigned(15 downto 0);
         REGMUX: in bit;         
         REGMUX_out: out unsigned(15 downto 0));
     end entity REGMUX_logic;
     
architecture build of REGMUX_logic is
    begin
        process(REGMUX,IR_out(7),BUS_in,SR1val)
            begin
                if REGMUX = '0' then-- and IR_out(7) = '0' then
                    REGMUX_out <= BUS_in;
                elsif REGMUX = '1' and IR_out(7) = '0' then
                    REGMUX_out <= SR1val + 2;
                elsif REGMUX = '1' and IR_out(7) = '1' then
                    REGMUX_out <= SR1val - 2;
                end if;
            end process;
    end build;
